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H O M E - APOLLO181 INTRODUCTION
Binary Clock Algorithm
Shift-and-Add Multiplication
Prime Numbers Benchmark
PWM LED Dimmer
Step Motor Controller
Sound Generator: Part 1
Sound Generator: Part 2
Random Number Generator

 

"BM9" benchmark: a crude routine to find out Prime Numbers

 

In order to evaluate APOLLO181 capability, I have succeeded to implement on it  a benchmark program that was originally written in BASIC: this is “BM9”, a very intensive algorithm for calculating prime numbers, which uses loops and computes long divisions.

A prime number is a natural number that has exactly two distinct natural number divisors: 1 and itself. For example, there are 25 prime numbers from 1 to 100: 2, 3, 5, 7, 11, 13, 17, 19, 23, 29, 31, 37, 41, 43, 47, 53, 59, 61, 67, 71, 73, 79, 83, 89, 97.

 

The formal “Benchmark BM9”, given by Tom Fox in the June 1980 issue of “Interface Age”, consisted in printing to the screen prime numbers in the range 1 to 1000, calculated in an outer loop of 1000 and an inner loop of 500, with no workarounds at all.

  

A series of nine benchmarks, including "BM9", were presented by Dr. M. R. Wigan at the 1982 MICSIG conference in Canberra, August 18-20 and reprinted in: “BASIC, FORTRAN, S-ALGOL and Pascal Benchmarks on microcomputers, including the effects of floating point processor support” by M. R. Wigan, Oxford Systematics, PO Box 281, Mt Waverley, Victoria 3149, Australia.

Photo Source: Control Data Corporation Advertising
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CDC CYBER Supercomputer run benchmark BM9 in 5 seconds in BASIC: an outstanding performance

"BM9 benchmark", intentionally wasteful, is particularly interesting because it was run on several of the most popular computers in late ‘70s and early ‘80s to compare high-level languages (interpreters and compilers) using different system configurations at different clock rates and supplementary processors: the fastest tested machine was CDC CYBER, a late-1970s mainframe-class supercomputer, which run "BM9" (in Basic) in only 5 seconds! The slowest tested machine was TRS-80 Pocket Computer, which painfully run "BM9" in 55830 seconds. In total "BM9" was tested on more than sixty different machines and configurations.

 

Unfortunately we cannot directly compare APOLLO181's  "BM9" score with the published results.

 

Any benchmark published by Oxford Systematics in June 1982 was in fact implemented on mainframes, minicomputers and microcomputers in “high-level” language only (BASIC, FORTRAN, S-ALGOL and PASCAL) while in APOLLO181 it is directly written in machine code, in the form of binary bits. 

Compilers and interpreters are both used to translate high-level programming languages into machine code; interpreters are generally slower than compiled programs due to their per-line translation method; a compiler, even if it does fairly well in optimizing, it's going to generate coding structures which do a lot of unnecessary work. Writing in machine code should make programs to run fastest of all because machine code tends to be optimized for the hardware it is designed for. An expert programmer can always generate more performing machine code than a compiler: for example by better using registers and addressing modes, or avoiding from calling routines, or implementing more efficient algorithms to multiply and shift. 

 

Furthermore, the output of prime numbers on external monitor will slow down the execution speed of the benchmark on mainframes, minicomputers and microcomputers, while in APOLLO181 prime numbers are simply displayed in binary format by on-board leds.

 

For these reasons "BM9 benchmark" runs faster on APOLLO181, without suffering delays due to “high-level” language translators and due to screen handling routines; hence, it cannot be directly compared with the published results. In any case the minimal length of the algorithm (which I succeeded to accurately translate from PASCAL into only a couple hundred bytes in RAM), the correctness of the execution and the timing score, are very important to test APOLLO181 processor’s capability.

 

"BM9 benchmark", written in machine code, runs on APOLLO181 in about 56 seconds (@ 3MHz). The program occupies only 0.2 KByte of RAM and it is accomplished using a combination of only fourteen different binary instructions.

 

Even if not directly comparable, this result would rank APOLLO181 number six among all Oxford Systematics tested machines using BASIC, just slower than the 45 seconds of the DEC PDP 11/70, but much faster than any benchmark written in “high-level” languages on Apple II or on Z80 machines running at 2 or 4 MHz.

 

 

Herebelow the original Tom Fox “BM9 benchmark” routine written both in BASIC and in PASCAL (source: Oxford Systematics)

 

 

100 REM BM9                              (BASIC)

130 PRINT "BM9"

140 FOR N=1 TO 1000

150 FOR K= 2 TO 500

160 LET M=N/K

170 LET L=INT(M)

180 IF L=0 THEN 230

190 IF L=1 THEN 220

200 IF M>L THEN 220

210 IF M=L THEN 240

220 NEXT K

230 PRINT N;

240 NEXT N

250 PRINT "E"

260 END

 

program bm9;                              (PASCAL)

LABEL 1,2,3;

VAR k,l,m,n: integer;

BEGIN

writeln('bm9');

for n:=1 to 1000 do

BEGIN

for k:=2 to 500 do

BEGIN

m:=n mod k;

l:=n div k;

if l=0 then goto 2;

if l=1 then goto 1;

if m>0 then goto 1;

if m=0 then goto 3;

1:END;

2:writeln(n);

3:END;

write('e');

END.

 

 

In order to execute operations such as “N mod K” or “N div K”, we need to implement a division subroutine. Modulo operation is just equivalent to calculate the reminder of division of N by K.

 

Since the maximum integer number to handle is one thousand, a 12-bit unsigned integer division algorithm will be adequate. An efficient division subroutine to implement is the “Shift, Test and Restore algorithm", derived from the standard "pencil and paper" division technique and accomplished here via bit shifting and binary addition/subtraction.

 

Considering the standard "pencil and paper" way to divide two numbers, for example 71 (“100 0111”) divided by 13 (“1101”) equals to 5 with a reminder of 6:

 

 

1000111 : 1101 = 101 Quotient

10001-         

01101=   

______

00100

 

001001

 

0010011-

0001101= 

________

0000110   Remainder (or Rest) or Modulo

 

 

the algorithm to compute the Quotient and the Reminder in a binary division will be the following:

 

 

Clear Reminder register

 

For i = 1 to 12 do {using 12-bit representations}

{ Left Shift Reminder and Quotient pair registers

Subtract the Divisor from Reminder in order to determine whether

the Divisor is smaller than the partial Remainder

If Reminder is positive then

Set the low order (right most) bit in Quotient to 1

Else

Restore Reminder by adding back the Divisor

}

 

 

 

Working with APOLLO181, equipped with a single 74181 4-bit ALU:

 

12-bit left shifting, is performed by “A+A” arithmetic operation with carry propagation;

 

set low order bit to 1, is equivalent to make a

logic “OR” with word “0001”;

 

12-bit addition, is performed by “A+B” arithmetic operation with carry propagation; 

 

12-bit subtraction, is performed by “A-B” arithmetic operation with borrow propagation;

 

test if 12-bit register “K=0”, is performed by checking if logic “OR” among all nibbles returns zero;

 

test if 12-bit register “K>n”, is performed by checking if “n–K” subtraction returns a borrow.

 

 

 

In order to accurately translate the entire “BM9” statements from PASCAL into APOLLO181 instructions, we will need to use all the sixteen 4-bit registers, allocated as following:

 

R0 is a 4-bit register which contains the counter of cycles in the division subroutine (from 0 to 11, which counts the twelve times in which Reminder and Quotient are left-shifted one binary position).

 

R3&R2&R1 form a 12-bit register which contains the Dividend of the division that after the execution of the division subroutine will contain the Quotient Q, result of the division.

 

R6&R5&R4 form a 12-bit register which contains the Rest (Reminder) after the division subroutine, which is the same number as the result of Modulo operation.

 

R9&R8&R7 form a 12-bit register which contains the Divisor, which is the number that is dividing the dividend in the division subroutine.

 

RC&RB&RA form a 12-bit register which contains the N counter which is the control variable of the outer loop (For…Next Statement in Basic). The initial value of the counter is 1 and the final value is 1000 (or “3E8” in hexadecimal). The content of these registers is passed into R3&R2&R1 as Dividend, before executing the division subroutine.

 

RF&RE&RD form a 12-bit register which contains the K counter which is the control variable of the inner loop (For…Next statement in Basic). The initial value of the counter is 2 and the final value is 500 (or “1F4” in hexadecimal). The content of these registers is passed into R9&R8&R7 as Divisor, before executing the division subroutine.

 

Here below the “BM9” algorithm which I have rewritten and suited for APOLLO181:

 

Address   Description          APOLLO181 Code

 

00

PRINT "BM9"

14

ACC = 4#

01

B=ASCII CODE 066

FA

OUT PORT [A] = ACC

02

M=ASCII CODE 077

12

ACC = 2#

03

9=ASCII CODE 057

F9

OUT PORT [9] = ACC

04

 

14

ACC = 4#

05

 

F8

OUT PORT [8] = ACC

06

 

1D

ACC = D#

07

 

F7

OUT PORT [7] = ACC

08

 

13

ACC = 3#

09

 

F8

OUT PORT [8] = ACC

0A

 

19

ACC = 9#

0B

 

F7

OUT PORT [7] = ACC

0C

 

10

ACC = 0#

0D

 

F9

OUT PORT [9] = ACC

0E

 

FA

OUT PORT [A] = ACC

0F

LET N=1

11

ACC = 1#

10

N: RC&RB&RA

2A

REG [A] = ACC

11

 

10

ACC = 0#

12

 

2B

REG [B] = ACC

13

 

2C

REG [C] = ACC

14

LET K=2

12

ACC = 2#

15

K: RF&RE&RD

2D

REG [D] = ACC

16

 

10

ACC = 0#

17

 

2E

REG [E] = ACC

18

 

2F

REG [F] = ACC

19

START INTEGER DIVISION routine

3A

ACC = REG [A]

1A

L=N/K; Rest=N MOD K

21

REG [1] = ACC

1B

Q=Q/DIV with Rest

3B

ACC = REG [B]

1C

LET Q=N

22

REG [2] = ACC

1D

N: RC&RB&RA

3C

ACC = REG [C]

1E

Q: R3&R2&R1

23

REG [3] = ACC

1F

LET DIV=K

3D

ACC = REG [D]

20

K: RF&RE&RD

27

REG [7] = ACC

21

DIV: R9&R8&R7

3E

ACC = REG [E]

22

 

28

REG [8] = ACC

23

 

3F

ACC = REG [F]

24

 

29

REG [9] = ACC

25

TEST IF DIV is Zero

4E

SET ALU to E#

26

 

37

ACC = REG [7]

27

 

88

ACC = Logic f(ACC, REG8)

28

 

89

ACC = Logic f(ACC, REG9)

29

 

A0

Compare ACC with 0#

2A

 

1A

ACC = A#

2B

IF DIV is Zero than GOTO ERROR

CC

IF ZERO GOTO CA#

2C

Clear Rest

10

ACC = 0#

2D

Rest: R6&R5&R4

24

REG [4] = ACC

2E

 

25

REG [5] = ACC

2F

 

26

REG [6] = ACC

30

FOR Counter = 11 TO 0 (12 Cycles)

1B

ACC = B#

31

Counter: R0

20

REG [0] = ACC

32

SHIFT LEFT Rest&Q pair

90

SET NO CARRY

33

Rest&Q: R6&R5&R4&R3&R2&R1

4C

SET ALU to C#

34

 

31

ACC = REG [1]

35

 

50

ACC = Arithm f(ACC, 0#, CARRY)

36

 

21

REG [1] = ACC

37

 

32

ACC = REG [2]

38

 

50

ACC = Arithm f(ACC, 0#, CARRY)

39

 

22

REG [2] = ACC

3A

 

33

ACC = REG [3]

3B

 

50

ACC = Arithm f(ACC, 0#, CARRY)

3C

 

23

REG [3] = ACC

3D

 

34

ACC = REG [4]

3E

 

50

ACC = Arithm f(ACC, 0#, CARRY)

3F

 

24

REG [4] = ACC

40

 

35

ACC = REG [5]

41

 

50

ACC = Arithm f(ACC, 0#, CARRY)

42

 

25

REG [5] = ACC

43

 

36

ACC = REG [6]

44

 

50

ACC = Arithm f(ACC, 0#, CARRY)

45

 

26

REG [6] = ACC

46

Rest=Rest-DIV

9F

SET WITH CARRY

47

R6&R5&R4= R6&R5&R4 - R9&R8&R7

46

SET ALU to 6#

48

 

34

ACC = REG [4]

49

 

67

ACC = Arithm f(ACC, REG7, CARRY)

4A

 

24

REG [4] = ACC

4B

 

35

ACC = REG [5]

4C

 

68

ACC = Arithm f(ACC, REG8, CARRY)

4D

 

25

REG [5] = ACC

4E

 

36

ACC = REG [6]

4F

 

69

ACC = Arithm f(ACC, REG9, CARRY)

50

 

26

REG [6] = ACC

51

 

10

ACC = 0#

52

IF Rest >=0 GOTO 60#

D6

IF CARRY GOTO 60#

53

IF Rest <0 Restore Rest

90

SET NO CARRY

54

Rest = Rest + DIV

49

SET ALU to 9#

55

R6&R5&R4= R6&R5&R4 + R9&R8&R7

34

ACC = REG [4]

56

 

67

ACC = Arithm f(ACC, REG7, CARRY)

57

 

24

REG [4] = ACC

58

 

35

ACC = REG [5]

59

 

68

ACC = Arithm f(ACC, REG8, CARRY)

5A

 

25

REG [5] = ACC

5B

 

36

ACC = REG [6]

5C

 

69

ACC = Arithm f(ACC, REG9, CARRY)

5D

 

26

REG [6] = ACC

5E

 

14

ACC = 4#

5F

 

06

GOTO 64#

60

SET to 1 the LOW ORDER BIT in Q

4E

SET ALU to E#

61

 

31

ACC = REG [1]

62

 

71

ACC = Logic f(ACC, 1#)

63

 

21

REG [1] = ACC

64

Decrement Counter

90

SET NO CARRY

65

Counter: R0=R0-1

4F

SET ALU to F#

66

 

30

ACC = REG [0]

67

 

50

ACC = Arithm f(ACC, 0#, CARRY)

68

 

20

REG [0] = ACC

69

 

12

ACC = 2#

6A

NEXT Counter ( END DIVISION Routine)

D3

IF CARRY GOTO 32#

6B

TEST IF L=0

4E

SET ALU to E#

6C

L: Q: R3&R2&R1

33

ACC = REG [3]

6D

 

82

ACC = Logic f(ACC, REG2)

6E

 

81

ACC = Logic f(ACC, REG1)

6F

 

A0

Compare ACC with 0#

70

 

15

ACC = 5#

71

IF L=0 GOTO A5#

CA

IF ZERO GOTO A5#

72

TEST IF L=1

33

ACC = REG [3]

73

L: Q: R3&R2&R1

82

ACC = Logic f(ACC, REG2)

74

 

A0

Compare ACC with 0#

75

 

19

ACC = 9#

76

 

C7

IF ZERO GOTO 79#

77

 

1D

ACC = D#

78

IF L<>1 GOTO 7D#

07

GOTO 7D#

79

 

31

ACC = REG [1]

7A

 

A1

Compare ACC with 1#

7B

 

10

ACC = 0#

7C

IF L=1 GOTO 90#

C9

IF ZERO GOTO 90#

7D

TEST IF N MOD K >0 (TEST IF M>L)

9F

SET WITH CARRY

7E

TEST IF Rest>0

46

SET ALU to 6#

7F

Rest: R6&R5&R4

10

ACC = 0#

80

Do Zero minus Rest

64

ACC = Arithm f(ACC, REG4, CARRY)

81

 

10

ACC = 0#

82

 

65

ACC = Arithm f(ACC, REG5, CARRY)

83

 

10

ACC = 0#

84

 

66

ACC = Arithm f(ACC, REG6, CARRY)

85

IF M=L (IF Rest=0) GOTO 89#

19

ACC = 9#

86

 

D8

IF CARRY GOTO 89#

87

 

10

ACC = 0#

88

IF N MOD K >0 (IF M>L) GOTO 90#

C9

IF ZERO GOTO 90#

89

TEST IF N MOD K =0 (TEST IF M=L)

4E

SET ALU to E#

8A

TEST IF Rest=0

34

ACC = REG [4]

8B

Rest: R6&R5&R4

85

ACC = Logic f(ACC, REG5)

8C

 

86

ACC = Logic f(ACC, REG6)

8D

 

A0

Compare ACC with 0#

8E

 

1D

ACC = D#

8F

IF N MOD K =0 (IF M=L) GOTO AD#

CA

IF ZERO GOTO AD#

90

START NEXT K routine

90

SET NO CARRY

91

K=K+1

49

SET ALU to 9#

92

K: RF&RE&RD

3D

ACC = REG [D]

93

 

51

ACC = Arithm f(ACC, 1#, CARRY)

94

 

2D

REG [D] = ACC

95

 

3E

ACC = REG [E]

96

 

50

ACC = Arithm f(ACC, 0#, CARRY)

97

 

2E

REG [E] = ACC

98

 

3F

ACC = REG [F]

99

 

50

ACC = Arithm f(ACC, 0#, CARRY)

9A

 

2F

REG [F] = ACC

9B

TEST IF K>500

9F

SET WITH CARRY

9C

Do 500 minus K

46

SET ALU to 6#

9D

500d = 1F4h

14

ACC = 4#

9E

K: RF&RE&RD

6D

ACC = Arithm f(ACC, REGD, CARRY)

9F

 

1F

ACC = F#

A0

 

6E

ACC = Arithm f(ACC, REGE, CARRY)

A1

 

11

ACC = 1#

A2

 

6F

ACC = Arithm f(ACC, REGF, CARRY)

A3

 

19

ACC = 9#

A4

IF K <=500: NEXT K

D1

IF CARRY GOTO 19#

A5

PRINT N

3A

ACC = REG [A]

A6

N: RC&RB&RA

F7

OUT PORT [7] = ACC

A7

 

3B

ACC = REG [B]

A8

 

F8

OUT PORT [8] = ACC

A9

 

3C

ACC = REG [C]

AA

 

F9

OUT PORT [9] = ACC

AB

 

10

ACC = 0#

AC

 

FA

OUT PORT [A] = ACC

AD

START NEXT N routine

90

SET NO CARRY

AE

N=N+1

49

SET ALU to 9#

AF

N: RC&RB&RA

3A

ACC = REG [A]

B0

 

51

ACC = Arithm f(ACC, 1#, CARRY)

B1

 

2A

REG [A] = ACC

B2

 

3B

ACC = REG [B]

B3

 

50

ACC = Arithm f(ACC, 0#, CARRY)

B4

 

2B

REG [B] = ACC

B5

 

3C

ACC = REG [C]

B6

 

50

ACC = Arithm f(ACC, 0#, CARRY)

B7

 

2C

REG [C] = ACC

B8

TEST IF N>1000

9F

SET WITH CARRY

B9

Do 1000 minus N

46

SET ALU to 6#

BA

1000d = 3E8h

18

ACC = 8#

BB

N: RC&RB&RA

6A

ACC = Arithm f(ACC, REGA, CARRY)

BC

 

1E

ACC = E#

BD

 

6B

ACC = Arithm f(ACC, REGB, CARRY)

BE

 

13

ACC = 3#

BF

 

6C

ACC = Arithm f(ACC, REGC, CARRY)

C0

 

14

ACC = 4#

C1

IF N <=1000: NEXT N

D1

IF CARRY GOTO 14#

C2

PRINT "E"

14

ACC = 4#

C3

E=ASCII CODE 069

F8

OUT PORT [8] = ACC

C4

 

15

ACC = 5#

C5

 

F7

OUT PORT [7] = ACC

C6

 

10

ACC = 0#

C7

 

F9

OUT PORT [9] = ACC

C8

 

19

ACC = 9#

C9

END PROGRAM

0C

GOTO C9#

CA

ERROR routine

1F

ACC = F#

CB

 

F7

OUT PORT [7] = ACC

CC

 

F8

OUT PORT [8] = ACC

CD

 

F9

OUT PORT [9] = ACC

CE

 

FA

OUT PORT [A] = ACC

CF

 

10

ACC = 0#

D0

HALT

0D

GOTO D0#

 

Here the list of the 168 prime numbers up to 1000, in decimal and in binary format, which are the correct output of the “BM9” benchmark:

 

2
 0000   0000   0010
 
3
 0000   0000   0011
 
5
 0000   0000   0101
 
7
 0000   0000   0111
 
11
 0000   0000   1011
 
13
 0000   0000   1101
 
17
 0000   0001   0001
 
19
 0000   0001   0011
 
23
 0000   0001   0111
 
29
 0000   0001   1101
 
31
 0000   0001   1111
 
37
 0000   0010   0101
 
41
 0000   0010   1001
 
43
 0000   0010   1011
 
47
 0000   0010   1111
 
53
 0000   0011   0101
 
59
 0000   0011   1011
 
61
 0000   0011   1101
 
67
 0000   0100   0011
 
71
 0000   0100   0111
 
73
 0000   0100   1001
 
79
 0000   0100   1111
 
83
 0000   0101   0011
 
89
 0000   0101   1001
 
97
 0000   0110   0001
 
101
 0000   0110   0101
 
103
 0000   0110   0111
 
107
 0000   0110   1011
 
109
 0000   0110   1101
 
113
 0000   0111   0001
 
127
 0000   0111   1111
 
131
 0000   1000   0011
 
137
 0000   1000   1001
 
139
 0000   1000   1011
 
149
 0000   1001   0101
 
151
 0000   1001   0111
 
157
 0000   1001   1101
 
163
 0000   1010   0011
 
167
 0000   1010   0111
 
173
 0000   1010   1101
 
179
 0000   1011   0011
 
181
 0000   1011   0101
 
191
 0000   1011   1111
 
193
 0000   1100   0001
 
197
 0000   1100   0101
 
199
 0000   1100   0111
 
211
 0000   1101   0011
 
223
 0000   1101   1111
 
227
 0000   1110   0011
 
229
 0000   1110   0101
 
233
 0000   1110   1001
 
239
 0000   1110   1111
 
241
 0000   1111   0001
 
251
 0000   1111   1011
 
257
 0001   0000   0001
 
263
 0001   0000   0111
 
269
 0001   0000   1101
 
271
 0001   0000   1111
 
277
 0001   0001   0101
 
281
 0001   0001   1001
 
283
 0001   0001   1011
 
293
 0001   0010   0101
 
307
 0001   0011   0011
 
311
 0001   0011   0111
 
313
 0001   0011   1001
 
317
 0001   0011   1101
 
331
 0001   0100   1011
 
337
 0001   0101   0001
 
347
 0001   0101   1011
 
349
 0001   0101   1101
 
353
 0001   0110   0001
 
359
 0001   0110   0111
 
367
 0001   0110   1111
 
373
 0001   0111   0101
 
379
 0001   0111   1011
 
383
 0001   0111   1111
 
389
 0001   1000   0101
 
397
 0001   1000   1101
 
401
 0001   1001   0001
 
409
 0001   1001   1001
 
419
 0001   1010   0011
 
421
 0001   1010   0101
 
431
 0001   1010   1111
 
433
 0001   1011   0001
 
439
 0001   1011   0111
 
443
 0001   1011   1011
 
449
 0001   1100   0001
 
457
 0001   1100   1001
 
461
 0001   1100   1101
 
463
 0001   1100   1111
 
467
 0001   1101   0011
 
479
 0001   1101   1111
 
487
 0001   1110   0111
 
491
 0001   1110   1011
 
499
 0001   1111   0011
 
503
 0001   1111   0111
 
509
 0001   1111   1101
 
521
 0010   0000   1001
 
523
 0010   0000   1011
 
541
 0010   0001   1101
 
547
 0010   0010   0011
 
557
 0010   0010   1101
 
563
 0010   0011   0011
 
569
 0010   0011   1001
 
571
 0010   0011   1011
 
577
 0010   0100   0001
 
587
 0010   0100   1011
 
593
 0010   0101   0001
 
599
 0010   0101   0111
 
601
 0010   0101   1001
 
607
 0010   0101   1111
 
613
 0010   0110   0101
 
617
 0010   0110   1001
 
619
 0010   0110   1011
 
631
 0010   0111   0111
 
641
 0010   1000   0001
 
643
 0010   1000   0011
 
647
 0010   1000   0111
 
653
 0010   1000   1101
 
659
 0010   1001   0011
 
661
 0010   1001   0101
 
673
 0010   1010   0001
 
677
 0010   1010   0101
 
683
 0010   1010   1011
 
691
 0010   1011   0011
 
701
 0010   1011   1101
 
709
 0010   1100   0101
 
719
 0010   1100   1111
 
727
 0010   1101   0111
 
733
 0010   1101   1101
 
739
 0010   1110   0011
 
743
 0010   1110   0111
 
751
 0010   1110   1111
 
757
 0010   1111   0101
 
761
 0010   1111   1001
 
769
 0011   0000   0001
 
773
 0011   0000   0101
 
787
 0011   0001   0011
 
797
 0011   0001   1101
 
809
 0011   0010   1001
 
811
 0011   0010   1011
 
821
 0011   0011   0101
 
823
 0011   0011   0111
 
827
 0011   0011   1011
 
829
 0011   0011   1101
 
839
 0011   0100   0111
 
853
 0011   0101   0101
 
857
 0011   0101   1001
 
859
 0011   0101   1011
 
863
 0011   0101   1111
 
877
 0011   0110   1101
 
881
 0011   0111   0001
 
883
 0011   0111   0011
 
887
 0011   0111   0111
 
907
 0011   1000   1011
 
911
 0011   1000   1111
 
919
 0011   1001   0111
 
929
 0011   1010   0001
 
937
 0011   1010   1001
 
941
 0011   1010   1101
 
947
 0011   1011   0011
 
953
 0011   1011   1001
 
967
 0011   1100   0111
 
971
 0011   1100   1011
 
977
 0011   1101   0001
 
983
 0011   1101   0111
 
991
 0011   1101   1111
 
997
 0011   1110   0101

 

DISCLAIMER & CREDIT: All data here reproduced are for educational and non-commercial purpose, following fair-use guidelines.

This is an INDIPENDENT AND UNOFFICIAL hobby site. Either Dr. Peter R. Rony or the Blacksburg group or Computer History Museum (Mountain View, CA) or other third-party DO NOT HAVE ANY ASSOTIATION with this work.

Author G.G. DOESN'T EARN ANYTHING FROM ADVERTISEMENT. This site is not in the business of making money. This site is visible thanks to the Free Web Hosting Tripod Service, so it is ad-supported: advertisement contents, costs and revenues are full managed by the service itself. Author does not have any involvement in them. The advertising links in the Site pages and in the pop-up windows are not Author's property. They can change and the Author is non-responsible about their contents and working. The Author is not responsible about the linked sites.
The information presented here is just that: INFORMATION. Use it at your own risk and for only non commercial purpose. The information here presented is believed to be technically correct and everything presented on this site is done so in good faith. Anyhow you (the reader) are responsible for anything that you might do as a result of reading this article. You assume complete and total responsibility for your actions! Author is not responsible for any misuse or damage coming from the reading and using this information.

Text and images from original typewritten Bugbooks I and II in 1974 are permission courtesy of Dr. Peter R. Rony, the original author and sole copyright owner of the Bugbooks I, II, IIA, III, V, and VI.

The background image on the header of each page of the site is "Sunset over western South America" photographed on 12 April 2011 by an Expedition 27 crew member on the International Space Station. (Image credit: NASA). On it I have merged titles and a my photo of TIL302 displays.

Texas Instruments data are Texas Instruments Copyright and reported by Courtesy of Texas Instruments.

 

TERM OF USE: With clear exception for texts and images which are not author's property, Gianluca G. freely authorizes you the downloading, printing and reproducing of APOLLO181 data, texts and images ONLY for non-commercial usage and ONLY if you give a clear reference to its source and project namewithout any right to resell or redistribute them or to compile or create derivative works.

Any rights not expressly granted herein are reserved.

 

Copyright (c) 2012 by Gianluca G. Italy