Controlling a Stepper Motor with APOLLO181

Simple controller for a stepper motor

The unipolar 12 VDC stepper motor is driven by TTL signals using NPN transistors and Mosfets

Stepper motors are electromagnetic actuators which convert electrical pulses into incremental mechanical movements. They operate differently from other DC motors that simply spin when voltage is applied. The shaft of a stepping motor rotates with a fixed step angle and without the need for position feedback. Motion is very precise in both directions even if running open loop.

The direction of the rotation, the speed and the final position of the shaft are in fact determined by the right sequence and polarity of the electrical pulses applied to the coils: speed is directly related to the frequency of the pulses, position is proportional to the number of the pulses and direction is commanded by the proper switching sequence of the pulses.

There are several designs of stepper motors. The one used here, taken from a printer, is a five-wire stepper motor designed for unipolar drive with all four commons joined together. The four coils (or four phases) work at 12 VDC and the construction of the permanent magnet rotor allows a shaft rotation of 7,5 degrees per step, so it requires 48 pulses (steps) to complete a full 360 degree rotation.

In a stepper motor the shape of the speed–torque characteristic curve can change quite considerably depending on both the type of the driver used (hardware and software) and the load inertia. In this exercise the load inertia is deliberately negligible (just a wheel indicator of shaft position). The hardware for each of the four phases consists of a NPN BJT which drives N-channel MOSFET into saturation: in fact with some power MOSFETs, the TTL voltage might be insufficient to fully turn on the device. The NPN allows interfacing the TTL logic level coming out from APOLLO181 output port to the higher working voltage of the motor board which requires an external 12 Volt, 1 Amp DC, power supply. When the bipolar transistor is OFF, the MOSFET gate potential rises to +12V. This will completely turn ON the MOSFET. If the bipolar transistor is turned ON, the MOSFET gate's potential will drop to VCE(SAT) = 0,2V. This will completely turn OFF the MOSFET.

Unfortunately the disadvantage of this practical circuit is that the TTL input signal is inverted by the NPN. A "logical zero" at the input turns ON the MOSFET and energises the winding of the stepper motor phase to cause the shaft to advance through the stepping. This can cause some confusion during the implementation of the algorithm.

Click to enlarge

Stepper motor driver board schematic

In this exercise APOLLO181 will drive the stepper motor in two ways. The first, basic, is the “full step” method in which only one phase is energized at a time and at 100% of current (i.e. on-off status).

	Phase 1	Phase 2	Phase 3	Phase 4
Step 1	ON	OFF	OFF	OFF
Step 2	OFF	ON	OFF	OFF
Step 3	OFF	OFF	ON	OFF
Step 4	OFF	OFF	OFF	ON

Remembering that input signals will be inverted by the motor circuit board, we will need the following “nibble” sequence at the output port of APOLLO181 for one shaft rotating direction:

	Bit 1	Bit 2	Bit 3	Bit 4
Step 1	0	1	1	1
Step 2	1	0	1	1
Step 3	1	1	0	1
Step 4	1	1	1	0

and the following “nibble“ sequence to rotate in the other direction:

	Bit 1	Bit 2	Bit 3	Bit 4
Step 1	0	1	1	1
Step 2	1	1	1	0
Step 3	1	1	0	1
Step 4	1	0	1	1

In full stepping method the coils are sequentially energised at 100% of current

The second implemented driving mode is more complex. It is the “half-step technique with compensated torque”. In the common half-step method we have only a single phase ON in one step, and a couple of phases ON in the next step: in this way we have low torque in one step and excessive power consumption in the following step. In order to compensate the higher torque on every half-step we need to apply a lower current to both the coils when they are simultaneously energised: if instead of applying full current, we energise both coils with the 71% of the current, we will get the same weaker torque as during the one phase ON step.

The formula for calculating the current in a n-stepping configuration are:

I_Ph1 = SIN (Step_number * 360° / Steps_total) * Imax =

= SIN (Step_number * 360° / 8) * Imax =

= SIN (360° / 8) * Imax = SIN (45°)* Imax = 0,71 * Imax = 71% Imax

I_Ph2 = COS (Step_number * 360° / Steps_total) * Imax =

= COS (Step_number * 360° / 8) * Imax =

= COS (360° / 8) * Imax = COS (45°)* Imax = 0,71 * Imax = 71% Imax

This requires input signals with three possible different current levels per phase: 0% (i.e OFF), 71% and 100% (i.e. full ON).

	Phase 1	Phase 2	Phase 3	Phase 4
Step 1	71%	71%	0%	0%
Step 2	0%	100%	0%	0%
Step 3	0%	71%	71%	0%
Step 4	0%	0%	100%	0%
Step 5	0%	0%	71%	71%
Step 6	0%	0%	0%	100%
Step 7	71%	0%	0%	71%
Step 8	100%	0%	0%	0%

In half-step compensated mode both coils energized at 71% equal torque on every half step

If we wish to energise the coils at 71% current, we can build via software a signal with duty cycle (DC) equal to 29% (in fact input signals will be inverted by the motor board circuit).

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Step 8

DC=71%

OFF

OFF

OFF

OFF

OFF

DC=71%

ON

Phase 1

DC=71%

ON

DC=71%

OFF

OFF

OFF

OFF

OFF

Phase 2

OFF

OFF

DC=71%

ON

DC=71%

OFF

OFF

OFF

Phase 3

OFF

OFF

OFF

OFF

DC=71%

ON

DC=71%

OFF

Phase 4

The following diagram is exactly the same as the previous one, but inverted to take care of the mosfet inverter driver.

Step 1

Step 2

Step 3

Step 4

Step 5

Step 6

Step 7

Step 8

DC=29%

ON

ON

ON

ON

ON

DC=29%

OFF

Output bit 1

DC=29%

OFF

DC=29%

ON

ON

ON

ON

ON

Output bit 2

ON

ON

DC=29%

OFF

DC=29%

ON

ON

ON

Output bit 3

ON

ON

ON

ON

DC=29%

OFF

DC=29%

ON

Output bit 4

In order to simplify the algorithm and reach higher speed rotation we will keep the DC at 4-bit of resolution. This allows 16 possible values of duty cycle according to the following table. In order to generate a DC approximately equal to 29%, we need to rise ON the signal for five sixteenths of the time and to fall the signal OFF for the rest eleven sixteenths of the time implementing via software a 4-bit delay loop.

~29% DC	Duty	4-bit	Counter
Duty Cycle	Cycle	Resolution	Binary
Shape	%	Value	Value

ON	0%	0	0000
ON	7%	1	0001
ON	13%	2	0010
ON	20%	3	0011
ON	27%	4	0100
OFF	33%	5	0101
OFF	40%	6	0110
OFF	47%	7	0111
OFF	53%	8	1000
OFF	60%	9	1001
OFF	67%	10	1010
OFF	73%	11	1011
OFF	80%	12	1100
OFF	87%	13	1101
OFF	93%	14	1110
OFF	100%	15	1111

The wished APOLLO181 output signal needed to energise both the coils during any half-step position is the following:

~ 29%

~71%

OFF

from 0 to 4

from 5 to 15

4-bit Delay Counter

Step 1

Here below the sequence of [(5+11)]*8= 128 nibbles that needs to be generated from APOLLO181 output port to rotate the shaft for 8 half-steps with compensated torque: remember that the nibble “1111” will put OFF the four coils of the motor, while, for example, “0111” will energise just the first coil. If you need to rotate in the other direction, you have to reverse the order of the commands in the list. Since this is a 7,5 degree stepping motor which needs 48 steps per revolution (or 96 half-steps per revolution), the sequence in the table must be repeated 96/8= 12 times to perform a complete shaft revolution (at the end we need to generate 128*12 = 1536 nibbles per revolution).

Time

Step1

Step2

Step3

Step4

Step5

Step6

Step7

Step8

1

1111

1011

1111

1101

1111

1110

1111

0111

2

1111

1011

1111

1101

1111

1110

1111

0111

3

1111

1011

1111

1101

1111

1110

1111

0111

4

1111

1011

1111

1101

1111

1110

1111

0111

5

1111

1011

1111

1101

1111

1110

1111

0111

6

0011

1011

1001

1101

1100

1110

0110

0111

7

0011

1011

1001

1101

1100

1110

0110

0111

8

0011

1011

1001

1101

1100

1110

0110

0111

9

0011

1011

1001

1101

1100

1110

0110

0111

10

0011

1011

1001

1101

1100

1110

0110

0111

11

0011

1011

1001

1101

1100

1110

0110

0111

12

0011

1011

1001

1101

1100

1110

0110

0111

13

0011

1011

1001

1101

1100

1110

0110

0111

14

0011

1011

1001

1101

1100

1110

0110

0111

15

0011

1011

1001

1101

1100

1110

0110

0111

16

0011

1011

1001

1101

1100

1110

0110

0111

I have implemented in APOLLO181 a 4-bit I/O port to control a stepper motor

The "full step" algorithm

The full step algorithm is easy to implement due to the unique structure of the nibble output. Main steps are the follow:

1) RA = “0111” (motor inputs are inverted, only one phase is energized at a time)

2) Set rotation direction (clockwise or not)

3) Set rotation speed (4-bit delay precision)

4) Set for “one turn” or “unlimited turns”

5) Output RA

6) Wait for Delay

7) Rotate RA right or left according to direction

8) Increment counter: Step = Step+1

9) If “one turn” Goto 12

10) If Step = 48 than Step = 0 (clear counter)

11) Goto 2

12) If Step = 48 than output “1111” (no phase is energized) and STOP

13) Goto 2

The trick is to use only one register (RA) to output the nibble to the motor board and then ROTATE the register LEFT or RIGHT at any step. We have already seen the 74181 rotation capability by using the following commands:

ROTATE RIGHT:

ACC = REG [A]

SET WITH CARRY

SET ALU to 1#

ACC = Arithm f (ACC, E#, CARRY) : A OR “1110” +Carry

ACC = REG [A]

SET ALU to C#

ACC = Arithm f (ACC, 0#, CARRY) : A+A+Carry

REG [A] = ACC

ROTATE LEFT:

ACC = REG [A]

SET NO CARRY

SET ALU to C#

ACC = Arithm f (ACC, 0#, CARRY) : A+A+Carry

SET ALU to 0#

ACC = Arithm f (ACC, 0#, CARRY) : A+Carry

REG [A] = ACC

As you can see, the two ROTATE algorithms are not the same length so we need to put some dummy operations (NOP commands or repeated) in order to run the algorithms at the same speed regardless of the direction of rotation.

Here the complete software:

00 17 ACC = 7#

01 2A REG [A] = ACC

02 10 ACC = 0#

03 26 REG [6] = ACC

04 1F ACC = F#

05 2E REG [E] = ACC

06 2F REG [F] = ACC

07 F8 OUT PORT [8] = ACC

08 F9 OUT PORT [9] = ACC

09 E8 ACC = IN PORT [8]

0A 28 REG [8] = ACC

0B E7 ACC = IN PORT [7]

0C F7 OUT PORT [7] = ACC

0D 21 REG [1] = ACC

0E 38 ACC = REG [8]

0F 4B SET ALU to B#

10 71 ACC = Logic f (ACC, 1#)

11 A0 Compare ACC with 0#

12 16 ACC = 6#

13 C1 IF ZERO GOTO 16#

14 1F ACC = F#

15 04 GOTO 4F#

16 3A ACC = REG [A]

17 FA OUT PORT [A] = ACC

18 F0 OUT PORT [0] = ACC

19 49 SET ALU to 9#

1A 10 ACC = 0#

1B 23 REG [3] = ACC

1C 90 SET NO CARRY

1D 10 ACC = 0#

1E 27 REG [7] = ACC

1F 37 ACC = REG [7]

20 51 ACC = Arithm f (ACC, 1#, CARRY)

21 27 REG [7] = ACC

22 16 ACC = 6#

23 D2 IF CARRY GOTO 26#

24 1F ACC = F#

25 01 GOTO 1F#

26 90 SET NO CARRY

27 33 ACC = REG [3]

28 AF Compare ACC with F#

29 14 ACC = 4#

2A C4 IF ZERO GOTO 44#

2B 33 ACC = REG [3]

2C 51 ACC = Arithm f (ACC, 1#, CARRY)

2D 23 REG [3] = ACC

2E 31 ACC = REG [1]

2F 24 REG [4] = ACC

30 90 SET NO CARRY

31 36 ACC = REG [6]

32 25 REG [5] = ACC

33 35 ACC = REG [5]

34 51 ACC = Arithm f (ACC, 1#, CARRY)

35 25 REG [5] = ACC

36 1A ACC = A#

37 D3 IF CARRY GOTO 3A#

38 13 ACC = 3#

39 03 GOTO 33#

3A 90 SET NO CARRY

3B 34 ACC = REG [4]

3C 51 ACC = Arithm f (ACC, 1#, CARRY)

3D 24 REG [4] = ACC

3E 12 ACC = 2#

3F D4 IF CARRY GOTO 42#

40 10 ACC = 0#

41 03 GOTO 30#

42 1C ACC = C#

43 01 GOTO 1C#

44 3A ACC = REG [A]

45 90 SET NO CARRY

46 4C SET ALU to C#

47 50 ACC = Arithm f (ACC, 0#, CARRY)

48 40 SET ALU to 0#

49 50 ACC = Arithm f (ACC, 0#, CARRY)

4A 2A REG [A] = ACC

4B 2A REG [A] = ACC

4C 2A REG [A] = ACC

4D 18 ACC = 8#

4E 08 GOTO 88#

4F 3A ACC = REG [A]

50 FA OUT PORT [A] = ACC

51 F0 OUT PORT [0] = ACC

52 49 SET ALU to 9#

53 10 ACC = 0#

54 23 REG [3] = ACC

55 90 SET NO CARRY

56 10 ACC = 0#

57 27 REG [7] = ACC

58 37 ACC = REG [7]

59 51 ACC = Arithm f (ACC, 1#, CARRY)

5A 27 REG [7] = ACC

5B 1F ACC = F#

5C D5 IF CARRY GOTO 5F#

5D 18 ACC = 8#

5E 05 GOTO 58#

5F 90 SET NO CARRY

60 33 ACC = REG [3]

61 AF Compare ACC with F#

62 1D ACC = D#

63 C7 IF ZERO GOTO 7D#

64 33 ACC = REG [3]

65 51 ACC = Arithm f (ACC, 1#, CARRY)

66 23 REG [3] = ACC

67 31 ACC = REG [1]

68 24 REG [4] = ACC

69 90 SET NO CARRY

6A 36 ACC = REG [6]

6B 25 REG [5] = ACC

6C 35 ACC = REG [5]

6D 51 ACC = Arithm f (ACC, 1#, CARRY)

6E 25 REG [5] = ACC

6F 13 ACC = 3#

70 D7 IF CARRY GOTO 73#

71 1C ACC = C#

72 06 GOTO 6C#

73 90 SET NO CARRY

74 34 ACC = REG [4]

75 51 ACC = Arithm f (ACC, 1#, CARRY)

76 24 REG [4] = ACC

77 1B ACC = B#

78 D7 IF CARRY GOTO 7B#

79 19 ACC = 9#

7A 06 GOTO 69#

7B 15 ACC = 5#

7C 05 GOTO 55#

7D 3A ACC = REG [A]

7E 9F SET WITH CARRY

7F 41 SET ALU to 1#

80 5E ACC = Arithm f (ACC, E#, CARRY)

81 3A ACC = REG [A]

82 4C SET ALU to C#

83 50 ACC = Arithm f (ACC, 0#, CARRY)

84 50 ACC = Arithm f (ACC, 0#, CARRY)

85 50 ACC = Arithm f (ACC, 0#, CARRY)

86 50 ACC = Arithm f (ACC, 0#, CARRY)

87 2A REG [A] = ACC

88 3E ACC = REG [E]

89 90 SET NO CARRY

8A 49 SET ALU to 9#

8B 51 ACC = Arithm f (ACC, 1#, CARRY)

8C 2E REG [E] = ACC

8D F8 OUT PORT [8] = ACC

8E 3F ACC = REG [F]

8F 40 SET ALU to 0#

90 50 ACC = Arithm f (ACC, 0#, CARRY)

91 2F REG [F] = ACC

92 F9 OUT PORT [9] = ACC

93 38 ACC = REG [8]

94 4B SET ALU to B#

95 72 ACC = Logic f (ACC, 2#)

96 A2 Compare ACC with 2#

97 1B ACC = B#

98 C9 IF ZERO GOTO 9B#

99 1F ACC = F#

9A 09 GOTO 9F#

9B 3F ACC = REG [F]

9C A3 Compare ACC with 3#

9D 15 ACC = 5#

9E CA IF ZERO GOTO A5#

9F 3F ACC = REG [F]

A0 A3 Compare ACC with 3#

A1 14 ACC = 4#

A2 C0 IF ZERO GOTO 04#

A3 1A ACC = A#

A4 0A GOTO AA#

A5 1F ACC = F#

A6 F0 OUT PORT [0] = ACC

A7 FA OUT PORT [A] = ACC

A8 19 ACC = 9#

A9 0A GOTO A9#

AA FF OUT PORT [F] = ACC

AB 19 ACC = 9#

AC 00 GOTO 09#

The "half-step technique with compensated torque" algorithm

The sequence of nibbles that needs to be generated from APOLLO181 output port to the motor board in order to rotate the shaft by half-steps with compensated torque is generated by the following steps:

1) RA = “1111” (motor input is inverted, no phase is energized)

2) RB = “0011” (motor input is inverted, two phases close together are energized at a time)

3) RC = “1011” (motor input is inverted, only one phase is energized at a time)

4) Set rotation speed (8-bit delay precision)

5) Output RA

6) Count with delay from 0 to 4

7) Rotate right RA (dummy)

8) Output RB

9) Count with delay from 0 to 10

10) Rotate right RB

11) Output RC

12) Count with delay from 0 to 15

13) Rotate right RC

14) Goto 4

Again, it was employed ROTATE function of the output register in order to save memory and used dummy repetitive commands to perform the sequence of the output with the proper and constant speed. Here the complete program for APOLLO181:

00 1F ACC = F#

01 2A REG [A] = ACC

02 13 ACC = 3#

03 2B REG [B] = ACC

04 1B ACC = B#

05 2C REG [C] = ACC

06 10 ACC = 0#

07 20 REG [0] = ACC

08 F9 OUT PORT [9] = ACC

09 E8 ACC = IN PORT [8]

0A F8 OUT PORT [8] = ACC

0B 26 REG [6] = ACC

0C E7 ACC = IN PORT [7]

0D F7 OUT PORT [7] = ACC

0E 21 REG [1] = ACC

0F 3A ACC = REG [A]

10 F0 OUT PORT [0] = ACC

11 FA OUT PORT [A] = ACC

12 49 SET ALU to 9#

13 30 ACC = REG [0]

14 23 REG [3] = ACC

15 90 SET NO CARRY

16 33 ACC = REG [3]

17 A5 Compare ACC with 5#

18 1E ACC = E#

19 C3 IF ZERO GOTO 3E#

1A 33 ACC = REG [3]

1B 51 ACC = Arithm f (ACC, 1#, CARRY)

1C 23 REG [3] = ACC

1D 31 ACC = REG [1]

1E 24 REG [4] = ACC

1F 90 SET NO CARRY

20 36 ACC = REG [6]

21 25 REG [5] = ACC

22 49 SET ALU to 9#

23 49 SET ALU to 9#

24 49 SET ALU to 9#

25 49 SET ALU to 9#

26 49 SET ALU to 9#

27 49 SET ALU to 9#

28 49 SET ALU to 9#

29 49 SET ALU to 9#

2A 49 SET ALU to 9#

2B 49 SET ALU to 9#

2C 49 SET ALU to 9#

2D 35 ACC = REG [5]

2E 51 ACC = Arithm f (ACC, 1#, CARRY)

2F 25 REG [5] = ACC

30 14 ACC = 4#

31 D3 IF CARRY GOTO 34#

32 12 ACC = 2#

33 02 GOTO 22#

34 90 SET NO CARRY

35 34 ACC = REG [4]

36 51 ACC = Arithm f (ACC, 1#, CARRY)

37 24 REG [4] = ACC

38 1C ACC = C#

39 D3 IF CARRY GOTO 3C#

3A 1F ACC = F#

3B 01 GOTO 1F#

3C 15 ACC = 5#

3D 01 GOTO 15#

3E 3A ACC = REG [A]

3F 9F SET WITH CARRY

40 41 SET ALU to 1#

41 5E ACC = Arithm f (ACC, E#, CARRY)

42 3A ACC = REG [A]

43 4C SET ALU to C#

44 50 ACC = Arithm f (ACC, 0#, CARRY)

45 50 ACC = Arithm f (ACC, 0#, CARRY)

46 50 ACC = Arithm f (ACC, 0#, CARRY)

47 50 ACC = Arithm f (ACC, 0#, CARRY)

48 50 ACC = Arithm f (ACC, 0#, CARRY)

49 2A REG [A] = ACC

4A 3B ACC = REG [B]

4B F0 OUT PORT [0] = ACC

4C FA OUT PORT [A] = ACC

4D 49 SET ALU to 9#

4E 30 ACC = REG [0]

4F 23 REG [3] = ACC

50 90 SET NO CARRY

51 33 ACC = REG [3]

52 AB Compare ACC with B#

53 19 ACC = 9#

54 C7 IF ZERO GOTO 79#

55 33 ACC = REG [3]

56 51 ACC = Arithm f (ACC, 1#, CARRY)

57 23 REG [3] = ACC

58 31 ACC = REG [1]

59 24 REG [4] = ACC

5A 90 SET NO CARRY

5B 36 ACC = REG [6]

5C 25 REG [5] = ACC

5D 49 SET ALU to 9#

5E 49 SET ALU to 9#

5F 49 SET ALU to 9#

60 49 SET ALU to 9#

61 49 SET ALU to 9#

62 49 SET ALU to 9#

63 49 SET ALU to 9#

64 49 SET ALU to 9#

65 49 SET ALU to 9#

66 49 SET ALU to 9#

67 49 SET ALU to 9#

68 35 ACC = REG [5]

69 51 ACC = Arithm f (ACC, 1#, CARRY)

6A 25 REG [5] = ACC

6B 1F ACC = F#

6C D6 IF CARRY GOTO 6F#

6D 1D ACC = D#

6E 05 GOTO 5D#

6F 90 SET NO CARRY

70 34 ACC = REG [4]

71 51 ACC = Arithm f (ACC, 1#, CARRY)

72 24 REG [4] = ACC

73 17 ACC = 7#

74 D7 IF CARRY GOTO 77#

75 1A ACC = A#

76 05 GOTO 5A#

77 10 ACC = 0#

78 05 GOTO 50#

79 3B ACC = REG [B]

7A 9F SET WITH CARRY

7B 41 SET ALU to 1#

7C 5E ACC = Arithm f (ACC, E#, CARRY)

7D 3B ACC = REG [B]

7E 4C SET ALU to C#

7F 50 ACC = Arithm f (ACC, 0#, CARRY)

80 50 ACC = Arithm f (ACC, 0#, CARRY)

81 50 ACC = Arithm f (ACC, 0#, CARRY)

82 50 ACC = Arithm f (ACC, 0#, CARRY)

83 2B REG [B] = ACC

84 2B REG [B] = ACC

85 3C ACC = REG [C]

86 F0 OUT PORT [0] = ACC

87 FA OUT PORT [A] = ACC

88 49 SET ALU to 9#

89 30 ACC = REG [0]

8A 23 REG [3] = ACC

8B 90 SET NO CARRY

8C 33 ACC = REG [3]

8D A5 Compare ACC with 5#

8E 14 ACC = 4#

8F CB IF ZERO GOTO B4#

90 33 ACC = REG [3]

91 51 ACC = Arithm f (ACC, 1#, CARRY)

92 23 REG [3] = ACC

93 31 ACC = REG [1]

94 24 REG [4] = ACC

95 90 SET NO CARRY

96 36 ACC = REG [6]

97 25 REG [5] = ACC

98 49 SET ALU to 9#

99 49 SET ALU to 9#

9A 49 SET ALU to 9#

9B 49 SET ALU to 9#

9C 49 SET ALU to 9#

9D 49 SET ALU to 9#

9E 49 SET ALU to 9#

9F 49 SET ALU to 9#

A0 49 SET ALU to 9#

A1 49 SET ALU to 9#

A2 49 SET ALU to 9#

A3 35 ACC = REG [5]

A4 51 ACC = Arithm f (ACC, 1#, CARRY)

A5 25 REG [5] = ACC

A6 1A ACC = A#

A7 DA IF CARRY GOTO AA#

A8 18 ACC = 8#

A9 09 GOTO 98#

AA 90 SET NO CARRY

AB 34 ACC = REG [4]

AC 51 ACC = Arithm f (ACC, 1#, CARRY)

AD 24 REG [4] = ACC

AE 12 ACC = 2#

AF DB IF CARRY GOTO B2#

B0 15 ACC = 5#

B1 09 GOTO 95#

B2 1B ACC = B#

B3 08 GOTO 8B#

B4 3C ACC = REG [C]

B5 9F SET WITH CARRY

B6 41 SET ALU to 1#

B7 5E ACC = Arithm f (ACC, E#, CARRY)

B8 3C ACC = REG [C]

B9 4C SET ALU to C#

BA 50 ACC = Arithm f (ACC, 0#, CARRY)

BB 50 ACC = Arithm f (ACC, 0#, CARRY)

BC 50 ACC = Arithm f (ACC, 0#, CARRY)

BD 50 ACC = Arithm f (ACC, 0#, CARRY)

BE 50 ACC = Arithm f (ACC, 0#, CARRY)

BF 2C REG [C] = ACC

C0 3C ACC = REG [C]

C1 F0 OUT PORT [0] = ACC

C2 FA OUT PORT [A] = ACC

C3 49 SET ALU to 9#

C4 10 ACC = 0#

C5 23 REG [3] = ACC

C6 90 SET NO CARRY

C7 33 ACC = REG [3]

C8 AB Compare ACC with B#

C9 1F ACC = F#

CA CE IF ZERO GOTO EF#

CB 33 ACC = REG [3]

CC 51 ACC = Arithm f (ACC, 1#, CARRY)

CD 23 REG [3] = ACC

CE 31 ACC = REG [1]

CF 24 REG [4] = ACC

D0 90 SET NO CARRY

D1 36 ACC = REG [6]

D2 25 REG [5] = ACC

D3 49 SET ALU to 9#

D4 49 SET ALU to 9#

D5 49 SET ALU to 9#

D6 49 SET ALU to 9#

D7 49 SET ALU to 9#

D8 49 SET ALU to 9#

D9 49 SET ALU to 9#

DA 49 SET ALU to 9#

DB 49 SET ALU to 9#

DC 49 SET ALU to 9#

DD 49 SET ALU to 9#

DE 35 ACC = REG [5]

DF 51 ACC = Arithm f (ACC, 1#, CARRY)

E0 25 REG [5] = ACC

E1 15 ACC = 5#

E2 DE IF CARRY GOTO E5#

E3 13 ACC = 3#

E4 0D GOTO D3#

E5 90 SET NO CARRY

E6 34 ACC = REG [4]

E7 51 ACC = Arithm f (ACC, 1#, CARRY)

E8 24 REG [4] = ACC

E9 1D ACC = D#

EA DE IF CARRY GOTO ED#

EB 10 ACC = 0#

EC 0D GOTO D0#

ED 16 ACC = 6#

EE 0C GOTO C6#

EF 3C ACC = REG [C]

F0 9F SET WITH CARRY

F1 41 SET ALU to 1#

F2 5E ACC = Arithm f (ACC, E#, CARRY)

F3 3C ACC = REG [C]

F4 4C SET ALU to C#

F5 50 ACC = Arithm f (ACC, 0#, CARRY)

F6 50 ACC = Arithm f (ACC, 0#, CARRY)

F7 50 ACC = Arithm f (ACC, 0#, CARRY)

F8 50 ACC = Arithm f (ACC, 0#, CARRY)

F9 2C REG [C] = ACC

FA 2C REG [C] = ACC

FB 1C ACC = C#

FC 00 GOTO 0C#

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This is an INDIPENDENT AND UNOFFICIAL hobby site. Either Dr. Peter R. Rony or the Blacksburg group or Computer History Museum (Mountain View, CA) or other third-party DO NOT HAVE ANY ASSOTIATION with this work.

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The information presented here is just that: INFORMATION. Use it at your own risk and for only non commercial purpose. The information here presented is believed to be technically correct and everything presented on this site is done so in good faith. Anyhow you (the reader) are responsible for anything that you might do as a result of reading this article. You assume complete and total responsibility for your actions! Author is not responsible for any misuse or damage coming from the reading and using this information.

Text and images from original typewritten Bugbooks I and II in 1974 are permission courtesy of Dr. Peter R. Rony, the original author and sole copyright owner of the Bugbooks I, II, IIA, III, V, and VI.

The background image on the header of each page of the site is "Sunset over western South America" photographed on 12 April 2011 by an Expedition 27 crew member on the International Space Station. (Image credit: NASA). On it I have merged titles and a my photo of TIL302 displays.

Texas Instruments data are Texas Instruments Copyright and reported by Courtesy of Texas Instruments.

TERM OF USE: With clear exception for texts and images which are not author's property, Gianluca G. freely authorizes you the downloading, printing and reproducing of APOLLO181 data, texts and images ONLY for non-commercial usage and ONLY if you give a clear reference to its source and project name, without any right to resell or redistribute them or to compile or create derivative works.

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Copyright (c) 2012 by Gianluca G. Italy